Computer Systems: Program... -Access
3rd Edition
ISBN: 9780134071923
Author: Bryant
Publisher: PEARSON
expand_more
expand_more
format_list_bulleted
Question
Chapter 4.5, Problem 4.35PP
Program Plan Intro
HCL code for d_valA signal:
word d_valA=[
D_icode in {ICALL,IJXX}:D_valP;
d_srcA == e_dstE:e_valE;
d_srcA == M_dstM:m_valM;
d_srcA == M_dstE:M_valE;
d_srcA == W_dstM:W_valM;
d_srcA == W_dstE:W_valE;
1:d_rvalA;
];
Processing stages:
- The processing of an instruction has number of operations.
- The operations are organized into particular sequence of stages.
- It attempts to follow a uniform sequence for all instructions.
- The description of stages are shown below:
- Fetch:
- It uses program counter “PC” as memory address to read instruction bytes from memory.
- The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.
- It fetches “valC” that denotes an 8-byte constant.
- It computes “valP” that denotes value of “PC” plus length of fetched instruction.
- Decode:
- The register file is been read with two operands.
- It gives values “valA” and “valB” for operands.
- It reads registers with instruction fields “rA” and “rB”.
- Execute:
- In this stage the ALU either performs required operation or increments and decrements stack pointer.
- The resulting value is termed as “valE”.
- The condition codes are evaluated and destination register is updated based on condition.
- It determines whether branch should be taken or not in a jump instruction.
- Memory:
- The data is been written to memory or read from memory in this stage.
- The value that is read is determined as “valM”.
- Write back:
- The results are been written to register file.
- It can write up to two results.
- PC update:
- The program counter “PC” denotes memory address to read bytes of instruction from memory.
- It is used to set next instruction’s address.
- Fetch:
Combinational circuits and HCL expressions:
- The computational blocks are been constructed by accumulating several logic gates into network.
- The restrictions are been shown below:
- Each of input for logic gate should be linked to any one shown below:
- One of system inputs, that is recognized as primary inputs.
- Output connection for some element in memory.
- Output of some logic gate.
- Outputs obtained from more than two logic gates could not be linked together.
- The wire would be driven to different voltages.
- It can cause malfunction in circuit.
- The network must not contain cycles.
- The loops in circuit can cause ambiguity in function
computed by network.
- The loops in circuit can cause ambiguity in function
- Each of input for logic gate should be linked to any one shown below:
- The “HCL” denotes a hardware control language that is used for describing control logic of different processor designs.
Expert Solution & Answer
Want to see the full answer?
Check out a sample textbook solutionStudents have asked these similar questions
Problem 4: Give a block diagram for a 8M x 32 memory using 512K x 8 memory ch book] [Hints: Figure 5.10 in the
1. We wish to compare the performance of two different machines: M1 and M2. The following measurements have been made on these machines:
Program
Time on M1
Time on M2
1
10 seconds
5 seconds
2
3 seconds
4 seconds
Which machine is faster for each program, and by how much?
2. For M1 and M2 of problem 1, the following additional measurements are made:. Find the instruction execution rate (instructions per second) for each machine when running program 1.
Program
Instructions executed on M1
Instructions executed on M2
1
200 x 106
160 x 106
3. For M1 and M2 of problem 1, if the clock rates are 200 MHz and 300 MHz, respectively, find the CPI for program 1 on both machines using the data provided in problems 1 and 2.
4. You are going to enhance a machine, and there are two possible improvements: either make multiply instructions run four times faster than before or make memory access instructions run two times faster than before. You…
Indicate the MIPS assembly corresponding to the following C blocks of code.
You can assume that the values of variables x and y are stored in registers R1 and R2, respectively. (a)
if (x==1) then
x+=5; else
x+=20;
(b)
for (int x=0; x<20; x++) y=y-2;
For block of code (b), show two solutions: one using only conditional branches, and one using also an unconditional branch (or jump). [7 for solution #1 + 7 for solution #2]Which assembly code is “better”? Why?
How can you easily distinguish a loop from an if-else-then block in an assembly program?
Chapter 4 Solutions
Computer Systems: Program... -Access
Ch. 4.1 - Prob. 4.1PPCh. 4.1 - Prob. 4.2PPCh. 4.1 - Prob. 4.3PPCh. 4.1 - Prob. 4.4PPCh. 4.1 - Prob. 4.5PPCh. 4.1 - Prob. 4.6PPCh. 4.1 - Prob. 4.7PPCh. 4.1 - Prob. 4.8PPCh. 4.2 - Practice Problem 4.9 (solution page 484) Write an...Ch. 4.2 - Prob. 4.10PP
Ch. 4.2 - Prob. 4.11PPCh. 4.2 - Prob. 4.12PPCh. 4.3 - Prob. 4.13PPCh. 4.3 - Prob. 4.14PPCh. 4.3 - Prob. 4.15PPCh. 4.3 - Prob. 4.16PPCh. 4.3 - Prob. 4.17PPCh. 4.3 - Prob. 4.18PPCh. 4.3 - Prob. 4.19PPCh. 4.3 - Prob. 4.20PPCh. 4.3 - Prob. 4.21PPCh. 4.3 - Prob. 4.22PPCh. 4.3 - Prob. 4.23PPCh. 4.3 - Prob. 4.24PPCh. 4.3 - Prob. 4.25PPCh. 4.3 - Prob. 4.26PPCh. 4.3 - Prob. 4.27PPCh. 4.4 - Prob. 4.28PPCh. 4.4 - Prob. 4.29PPCh. 4.5 - Prob. 4.30PPCh. 4.5 - Prob. 4.31PPCh. 4.5 - Prob. 4.32PPCh. 4.5 - Prob. 4.33PPCh. 4.5 - Prob. 4.34PPCh. 4.5 - Prob. 4.35PPCh. 4.5 - Prob. 4.36PPCh. 4.5 - Prob. 4.37PPCh. 4.5 - Prob. 4.38PPCh. 4.5 - Prob. 4.39PPCh. 4.5 - Prob. 4.40PPCh. 4.5 - Prob. 4.41PPCh. 4.5 - Prob. 4.42PPCh. 4.5 - Prob. 4.43PPCh. 4.5 - Prob. 4.44PPCh. 4 - Prob. 4.45HWCh. 4 - Prob. 4.46HWCh. 4 - Prob. 4.47HWCh. 4 - Prob. 4.48HWCh. 4 - Modify the code you wrote for Problem 4.47 to...Ch. 4 - In Section 3.6.8, we saw that a common way to...Ch. 4 - Prob. 4.51HWCh. 4 - The file seq-full.hcl contains the HCL description...Ch. 4 - Prob. 4.53HWCh. 4 - The file pie=full. hcl contains a copy of the PIPE...Ch. 4 - Prob. 4.55HWCh. 4 - Prob. 4.56HWCh. 4 - Prob. 4.57HWCh. 4 - Our pipelined design is a bit unrealistic in that...Ch. 4 - Prob. 4.59HW
Knowledge Booster
Similar questions
- 4.18 [5] <COD §4.5> Assume that X1 is initialized to 11 and X2 is initialized to 22. Suppose you executed the code below on a version of the pipeline from COD Section 4.5 (An overview of pipelining) that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). What would the final values of registers X3 and X4 be? ADDI X1, X2, #5 ADD X3, X1, X2 ADDI X4, X1, #15arrow_forward15.a) Consider an instruction pipeline with four stages with the stage delays 5 nsec, 6 nsec, 11 nsec, and 8 nsec respectively. The delay of an inter-stage register stage of the pipeline is 1 nsec. What is the approximate speedup of the pipeline in the steady-state underideal conditions as compared to the corresponding non-pipelined implementation? b) Discuss structural hazards and control hazards with examples pls answer both subparrts,,its urgent thanksarrow_forwardneed answer asap! Write the appropriate or instruction to reset bits 5 and 7 of register AX, and keep all others unchanged.arrow_forward
- Computer Science Consider the following comparison instruction:TST R0, R1, ASR #1 ; R0 = 0x12345678 and R1 = 0xDB97530F(i) Appraise the value of the condition flags (N, Z, C, V) after the execution of the instruction. Use the values of R0 and R1 provided in the instruction comment.(ii) The conditional branches are BHS, BLO, BLT and BPL. From the condition flag bits appraised in Question 2(b)(i), determine which of the above conditional branches will be executed.arrow_forwardQuestion 7: In the following instruction sequence, show the resulting value of AL where indicated, in Hexadecimal: a. mov al,7Ah not al ; . b. mov al,72h xor al,0DCh ; and also write instructions that first clear bit positions 0,1 and 2 in AL. Then, if the destination operand is equal to zero, the code should jump to label LABEL1. Otherwise, it should jump to label NEXTarrow_forwardWrite HCL code for the signal D_stall in the PIPE implementation.Pipeline register D must be set to bubble for a mispredicted branch ora ret instruction. As the analysis in the preceding section shows,however, it should not inject a bubble when there is a load/use hazardin combination with a ret instruction:bool D_bubble =# Mispredicted branch (E_icode == IJXX && !e_Cnd) ||# Stalling at fetch while ret passes through pipeline# but not condition for a load/use hazard!(E_icode in { IMRMOVQ, IPOPQ } && E_dstM in { d_srcA,d_srcB }) && IRET in { D_icode, E_icode, M_icode };arrow_forward
- COMPUTER ARCHITECTURE Question 1 Assume the following register conditions: AX = 9A1Ch, BX = 27C6h, CX = 3112h, DX = 4A1Ch Find the status of Carry Flag (CF), Parity Flag (PF), Auxiliary Flag (AF), Zero Flag (ZF), Overflow Flag (OF) and Sign Flag (SF) for the following operations (The operations are independent of each other.): i. MOV BL, 3Fh ADD BL, DAh ii. CMP BX, CX iii. NOT DX iv. ADD AX, DXarrow_forwardTopic : Writing MIPS code. 1.Consider the equation and write MIPS code for it: X=(A[4]+B[2])+(B[3]-5X); Assume array A stores floating-point values and its base address in $s0 and array B stores integer values and its base address is in $s1 register. X is in register $s2.arrow_forwardWe have three 4-bit registers A, B, and C available, each with the standard “Load” input. When “Load” is at 1, then 4-bit data available on the input of a register is loaded into the register at the next rising clock edge. Assume registers A and B are already loaded with 4-bit data representing unsigned numbers. We need to design the data path for the following case:If value stored in register A is an odd number, then register C should be loaded with the sum of values present in A and B registers; else, register C should be loaded with binary value 0000.Your design may include standard logic gates, adders, and multiplexers. PLEASE DRAW THE DIAGRAM WITH EXPLANATIONarrow_forward
- For a function with prototype long decode2(long x, long y, long z); GCC generates the following assembly code: 1 decode2: 2 subq %rdx, %rsi 3 imulq %rsi, %rdi 4 movq %rsi, %rax 5 salq $63, %rax 6 sarq $63, %rax 7 xorq %rdi, %rax 8 ret Parameters x, y, and z are passed in registers %rdi, %rsi, and %rdx. The code stores the return value in register %rax. Write C code for decode2 that will have an effect equivalent to the assembly code shown.arrow_forwardNote: I need only correct option with explanation. Don't give direct option and wrong answer. I'll give negative mark for wrong answer. Required correct option with explanation. If you don't know don't attempt forward to others.. Question: What is the maximum number of bits in PC that can change as a result of executing the MIPS instruction "add $1, $2, $3" ? a-30 b-28 c-26 d-32arrow_forwardI am trying to better understand memory access in computers, please answer the sample question below. Assume that the page table can held in registers of the MMU. It takes 8 ms (milliseconds)to service a page fault if there is an empty frame or if the replaced page is not altered, and20 ms if the replaced page is altered. Memory access time is 100 ns (nanoseconds). It has been empirically measured that the page to be replaced is altered 75% of the time.Obtain the maximum probability of page fault for an effective memory access time ≤ 200ns.arrow_forward
arrow_back_ios
SEE MORE QUESTIONS
arrow_forward_ios
Recommended textbooks for you
- Database System ConceptsComputer ScienceISBN:9780078022159Author:Abraham Silberschatz Professor, Henry F. Korth, S. SudarshanPublisher:McGraw-Hill EducationStarting Out with Python (4th Edition)Computer ScienceISBN:9780134444321Author:Tony GaddisPublisher:PEARSONDigital Fundamentals (11th Edition)Computer ScienceISBN:9780132737968Author:Thomas L. FloydPublisher:PEARSON
- C How to Program (8th Edition)Computer ScienceISBN:9780133976892Author:Paul J. Deitel, Harvey DeitelPublisher:PEARSONDatabase Systems: Design, Implementation, & Manag...Computer ScienceISBN:9781337627900Author:Carlos Coronel, Steven MorrisPublisher:Cengage LearningProgrammable Logic ControllersComputer ScienceISBN:9780073373843Author:Frank D. PetruzellaPublisher:McGraw-Hill Education
Database System Concepts
Computer Science
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:McGraw-Hill Education
Starting Out with Python (4th Edition)
Computer Science
ISBN:9780134444321
Author:Tony Gaddis
Publisher:PEARSON
Digital Fundamentals (11th Edition)
Computer Science
ISBN:9780132737968
Author:Thomas L. Floyd
Publisher:PEARSON
C How to Program (8th Edition)
Computer Science
ISBN:9780133976892
Author:Paul J. Deitel, Harvey Deitel
Publisher:PEARSON
Database Systems: Design, Implementation, & Manag...
Computer Science
ISBN:9781337627900
Author:Carlos Coronel, Steven Morris
Publisher:Cengage Learning
Programmable Logic Controllers
Computer Science
ISBN:9780073373843
Author:Frank D. Petruzella
Publisher:McGraw-Hill Education