Computer Systems: A Programmer's Perspective Plus Mastering Engineering With Pearson Etext -- Access Card Package (3rd Edition)
3rd Edition
ISBN: 9780134123837
Author: Randal E. Bryant, David R. O'Hallaron
Publisher: PEARSON
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Chapter 6, Problem 6.43HW
Program Plan Intro
Given Information:
The given code is:
//declaration of integer buffer
int *iptr= (int *) buffer;
//increment buffer pointer by iterating through buffer
for(; iptr<((int*)buffer)+ 640*480; iptr++)
//reassign the value of iptr as "0"
*iptr=0;
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Check out a sample textbook solutionStudents have asked these similar questions
Given that a 4-way set associative cache memory has 64 KB data and each block contains 32 bytes. The main memory capacity is 4 GB.
a. Find the number of bits for the main memory address. ANSWER:
bits
b. How many blocks are there in a set? ANSWER:
blocks
c. How many sets the cache has? ANSWER:
d. The main memory address format is => | Tag:
e. Which set will be mapped by the main memory address 458195h. ANSWER:
sets
bits | Set:
bits | Word:
bits |
(in decimal)
This chapter explains how to implement the four cache replacement policies.
Let's pretend that something unexpected happens: the CPU makes a partially-completed request to the cache at the same time as a block is being returned from the write buffer to main memory. The following steps need to take place.
Chapter 6 Solutions
Computer Systems: A Programmer's Perspective Plus Mastering Engineering With Pearson Etext -- Access Card Package (3rd Edition)
Ch. 6.1 - Prob. 6.1PPCh. 6.1 - Prob. 6.2PPCh. 6.1 - Prob. 6.3PPCh. 6.1 - Prob. 6.4PPCh. 6.1 - Prob. 6.5PPCh. 6.1 - Prob. 6.6PPCh. 6.2 - Prob. 6.7PPCh. 6.2 - Prob. 6.8PPCh. 6.4 - Prob. 6.9PPCh. 6.4 - Prob. 6.10PP
Ch. 6.4 - Prob. 6.11PPCh. 6.4 - Prob. 6.12PPCh. 6.4 - Prob. 6.13PPCh. 6.4 - Prob. 6.14PPCh. 6.4 - Prob. 6.15PPCh. 6.4 - Prob. 6.16PPCh. 6.5 - Prob. 6.17PPCh. 6.5 - Prob. 6.18PPCh. 6.5 - Prob. 6.19PPCh. 6.5 - Prob. 6.20PPCh. 6.6 - Prob. 6.21PPCh. 6 - Prob. 6.22HWCh. 6 - Prob. 6.23HWCh. 6 - Suppose that a 2 MB file consisting of 512-byte...Ch. 6 - The following table gives the parameters for a...Ch. 6 - The following table gives the parameters for a...Ch. 6 - Prob. 6.27HWCh. 6 - This problem concerns the cache in Practice...Ch. 6 - Suppose we have a system with the following...Ch. 6 - Suppose we have a system with following...Ch. 6 - Suppose that a program using the cache in Problem...Ch. 6 - Repeat Problem 6.31 for memory address0x16E8 A....Ch. 6 - Prob. 6.33HWCh. 6 - Prob. 6.34HWCh. 6 - Prob. 6.35HWCh. 6 - Prob. 6.36HWCh. 6 - Prob. 6.37HWCh. 6 - Prob. 6.38HWCh. 6 - Prob. 6.39HWCh. 6 - Given the assumptions in Problem 6.38, determine...Ch. 6 - You are writing a new 3D game that you hope will...Ch. 6 - Prob. 6.42HWCh. 6 - Prob. 6.43HWCh. 6 - Prob. 6.45HWCh. 6 - Prob. 6.46HW
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- For the cache design of the preceding problem, suppose that increasing the line size from one word to four words results in a decrease of the read miss rate from 3.2% to 1.1%. For both the nonburst transfer and the burst transfer case, what is the average miss penalty, averaged over all reads, for the two different line sizes?arrow_forwardFor the same 60 word fully associative cache with 30-word blocks, say the LRU replacement algorithm is used, and the LRU is always kept in index 0. And say you access the following 3 words, in the given order: 100, 120, 105 a) On the second access (the access of word 120), in which index will the block containing 120 be placed?arrow_forwardGiven that a 4-way set associative cache memory has 64 KB data and each block contains 32 bytes. The main memory capacity is 4 GB. a. Find the number of bits for the main memory address. ANSWER: b. How many blocks are there in a set? ANSWER: c. How many sets the cache has? ANSWER: d. The main memory address format is => | Tag: bits | blocks sets bits | Set: e. Which set will be mapped by the main memory address 458195h. ANSWER: decimal) bits bits | Word: (inarrow_forward
- Consider the best way to count how many bits are set in a bitmap. Keeping the size of the cache in mind, what are the trade-offs of choosing a smaller or larger array size?arrow_forwardConsider a fully-associative cache of size 4. Each slot in the cache can have just one item (i.e. the line size is 1 item). The cache is empty to start with. The cache uses an LRU replacement policy: every slot has a counter; every time a slot is accessed, a global counter is incremented and the value is stored in the slot counter; the slot with the lowest counter value is chosen for replacement. Sequence Id 1 2 3 4 5 6 7 8 10 Address Ox0012 0x0014 Ox0016 Ox0018 0x0016 0x0012 0x0020 Ox0022 0x0014 Ox0012 Hit/Miss Accesses 1 to 10 are respectively: Select one: O a. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, Miss O b. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Hit O. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Miss O d. Miss, Miss, Miss, Miss, Hit, Miss, Miss, Miss, Miss, Hit O e. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, Hitarrow_forwardA cache is set up with a block size of 8 words. There are 128 words in cache and set up to be direct map. You have word address 0x923. Show the word address, block address, tag, and index. Show each access being filled in with a note of hit or miss. You are given word address and the access are: 0xff, 0x08, 0x22, 0x00, 0x39, 0xF3, 0x07, 0xc0.arrow_forward
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