Computer Systems: A Programmer's Perspective Plus Mastering Engineering With Pearson Etext -- Access Card Package (3rd Edition)
Computer Systems: A Programmer's Perspective Plus Mastering Engineering With Pearson Etext -- Access Card Package (3rd Edition)
3rd Edition
ISBN: 9780134123837
Author: Randal E. Bryant, David R. O'Hallaron
Publisher: PEARSON
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Chapter 6, Problem 6.43HW
Program Plan Intro

Given Information:

The given code is:

//declaration of integer buffer

int *iptr= (int *) buffer;

//increment buffer pointer by iterating through buffer

for(; iptr<((int*)buffer)+ 640*480; iptr++)

//reassign the value of iptr as "0"

*iptr=0;

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Given that a 4-way set associative cache memory has 64 KB data and each block contains 32 bytes. The main memory capacity is 4 GB. a. Find the number of bits for the main memory address. ANSWER: bits b. How many blocks are there in a set? ANSWER: blocks c. How many sets the cache has? ANSWER: d. The main memory address format is => | Tag: e. Which set will be mapped by the main memory address 458195h. ANSWER: sets bits | Set: bits | Word: bits | (in decimal)
This chapter explains how to implement the four cache replacement policies.
Let's pretend that something unexpected happens: the CPU makes a partially-completed request to the cache at the same time as a block is being returned from the write buffer to main memory. The following steps need to take place.
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