A)
Explanation of Solution
Cache entry and cache byte:
The program running on a machine references the 1-byte word at address “
First, one needs to convert the hexadecimal address into binary form:
For example, “
One needs to consider the following set associative (S, E, B, m) = (8, 4, 4, 13). The derived value will be as follows:
The Index (CI):
B)
Explanation of Solution
Memory reference:
The address format (1 bit per box) for address “
CT | CT | CT | CT | CT | CT | CT | CT | CI | CI | CI | CO | CO |
0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 |
The memory reference for the above address format “
Want to see the full answer?
Check out a sample textbook solutionChapter 6 Solutions
Computer Systems: A Programmer's Perspective Plus Mastering Engineering With Pearson Etext -- Access Card Package (3rd Edition)
- Problem 0. The following table gives some of the parameters for a number of different hardware caches. Fill in the table with the values of the missing parameters. Recall that m is the number of physical address bits, C is the cache size in bytes, B is the block size in bytes, E is the associativity, i.e., lines per set, S is the number of sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits. Cache m 48 32030 (b) 48 32 24 24 C B E 16384 32 16 32768 64 65536 128 512 32 1024 8 8 4 14 1 4 S b S tarrow_forward(c) The following Sigma 16 program has been loaded into memory at address 0000: load R3,y[RO] load R4,x[RO] lea R5, 2[RO] sub R1,R4,R3 mul R2,R1,R5 store R2,w[RO] trap RO,RO,RO x data 10 y data 12 w data 0 Show the content of the memory writing hexadecimal representation and using a table with 3 columns: the memory address, the contents of that memory address, and an explanation of what "the content (of that memory address) means". As a reference, here are the opcodes for RRR instructions: add 0, sub 1, mul 2, trap c. And here the opcodes for RX instructions: lea 0, load 1, store 2. [7]arrow_forward(Part B) Design 32KW, 16-way set associative unblocked cache that has 8 bytes per word. Assume a 64 bit address. Calculate the following: (a) How many bits are used for the byte offset? (b) How many bits are used for the index field? (c) How many bits are used for the tag? (d) What is the physical size of each set (show as bits/row * # of rows, x * 2v)?arrow_forward
- (c) Assume that a Direct Mapping Function is apply on a memory system with 24-bit address. The cache has 16384 blocks, each storing 4 words. Calculate its tag, block, and word size.arrow_forward21. The idea of cache memory is based on a. The property of locality of reference b. The heuristic 90-10 rule c. The fact that only a small portion of a program is referenced relatively frequently d. None of thesearrow_forward< 5:37: Assembly Language Pro... Pointer Example ● • This is Example 4.4 from the textbook which demonstrates the use of the Loadl and Storel instructions to print a string • It is important to remember that at the assembly level, all I/O is character-based and only one character at a time can be sent to an output device Getch, Outp, One, Chptr, String, LoadI Chptr Skipcond 400 Jump Outp Halt Output Load Chptr Add One Store Chptr Jump Getch Hex 0001 Hex 00B Dec 072 Dec 101 Dec 108 Dec 108 Dec 111 Dec 032 Dec 119. Dec 111 Dec 114 Dec 108 Dec 100 Dec 033 Dec 000 /H /e /1 /1 / [space] /W /0 /r /1 /d /[null] LTE 100 D /Load the character found at /address Chptr /If AC = 0, skip next instruction /Otherwise, proceed with operation /Output the character /Move pointer to next character /Jump to "current" character /Pointer to "current" character /String definition starts herearrow_forward
- (5 points) A memory hierarchy has following hit rates and average access time (for sequential cache access) of CPU. Calculate the last hit rate. Hit Rate (%) 75 85 ??? Average Access Time of CPU (ns) 25 20 15arrow_forwardElectrical Engineering 1.) Consider the following series of address references, given as byte addresses: 4. 16, 32, 20, 80, 68, 76, 224, 36, 44, 16, 172, 20, 24, 36, 68 Label each reference as a hit or miss, and show the final cache contents, for each of the following caches. Assume LRU replacement (where appropriate). a.) Direct-mapped, 16x 4-byte blocks. b.) Direct-mapped, 16-byte blocks, total size of 64 bytes. c.) Two-way set associative, 4-byte blocks, total size of 64 bytes. d.) Fully associative, 4-byte blocks, total size of 64 bytes.arrow_forwardConsider the following C statement. Assume that the variables f and g are assigned to registers $s0 and $s1 respectively. Assume that the base address of the arrays A and B are in registers $s2 and $s3 respectively. Convert into MIPS code. B[1] = A[2] – (f + g)arrow_forward
- (Part C) Design 32KW, fully associative cache that has 4 32-bit words per block. Assume a 32. bit address. Calculate the following: (a) How many bits are used for the byte offset? (b) How many bits are used for the block offset? (c) How many bits are used for the index field? (d) How many bits are used for the tag? (e) What is the physical size of each set (show as bits/row * # of rows, x * 2V)?arrow_forward5. A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.arrow_forwardm ofessor, S. aw-Hill tion... V !!! ar textbook As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute a stream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number. TLB Page Table Decimal 4669 2227 13916 34587 48870 12608 49225 hex 0x123d 0x08b3 0x365c 0x871b Oxbee6 0x3140 0xc049 Valid 1 1 1 0 Index 0 1 2 3 4 5 (a) For each access shown above, list 6 7 8 9 a b Tag Oxb Ox7 0x3 0x4 Valid 1 0 0 1 1 1 0 1 0 0 1 1 ▪ whether the access is a hit or miss in the TLB, ▪ whether the access is a hit or miss in the page table, ▪ whether the access is a page fault, the updated state of the TLB. Physical Page Number 12 4 6 9 Time Since Last Access 4…arrow_forward
- C++ for Engineers and ScientistsComputer ScienceISBN:9781133187844Author:Bronson, Gary J.Publisher:Course Technology Ptr