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A)
Explanation of Solution
Cache entry and cache byte:
The program running on a machine references the 1-byte word at address “Ox0DD5”. Hexadecimal is a number system of base 16As and as hex system has 16 digits, the extra needed 6 digits are represented by the first 6 letters of English alphabet which means “ 0,1,2,3,4,5,6,7,8” represents “9,A,?B,?C,?D,?E,?F” respectively in decimal system.
First, one needs to convert the hexadecimal address into binary form:
One needs to consider the following set associative (S, E, B, m) = (8, 4, 4, 13). The derived value will be as follows:
The Index (CI):
B)
Explanation of Solution
Memory reference:
The address format (1 bit per box) for address “Ox0DD5” is hence represented as:
CT | CT | CT | CT | CT | CT | CT | CT | CI | CI | CI | CO | CO |
0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 |
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Chapter 6 Solutions
Computer Systems: A Programmer's Perspective Plus Mastering Engineering With Pearson Etext -- Access Card Package (3rd Edition)
- m ofessor, S. aw-Hill tion... V !!! ar textbook As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute a stream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number. TLB Page Table Decimal 4669 2227 13916 34587 48870 12608 49225 hex 0x123d 0x08b3 0x365c 0x871b Oxbee6 0x3140 0xc049 Valid 1 1 1 0 Index 0 1 2 3 4 5 (a) For each access shown above, list 6 7 8 9 a b Tag Oxb Ox7 0x3 0x4 Valid 1 0 0 1 1 1 0 1 0 0 1 1 ▪ whether the access is a hit or miss in the TLB, ▪ whether the access is a hit or miss in the page table, ▪ whether the access is a page fault, the updated state of the TLB. Physical Page Number 12 4 6 9 Time Since Last Access 4…arrow_forward3- What is the difference between: a- MOV BX,[1234H] and LEA BX,[1234H] b- LDS AX,[200H] and LES AXX,[200H] 4-Use MOV to load address of memory MEM1.arrow_forward[1] ( Show your work. Show hoe you compute memory address by using the effective memory address computation. Assume the following values are stored at the indicated memory addresses and registers: Address Value 0x100 OxFF 0x104 OxAB 0x108 0x13 0x10c 0x11 Register %rax %rcx %rdx $0x108 (%rax) 4(%rax) 9(%rax, %rdx) 260(%rcx,%rdx) OxFC (,%rcx, 4) (%rax, %rdx, 4) Value 0x100 0x1 0x3 Fill in the following table showing the values for the indicated operands: Operand Value %rax 0x104arrow_forward
- Problem Question 03 (CO3) [0.5 + 0.5 = 1]: Given below are the contents of several Intel 8086 registers and PHYSICAL memory addresses (ALL in hexadecimal): Registers: Memory Locations [Physical Address] = Contents [05000] = 3300 [06000] = 4444 [07000] = 5555 [95000] = 367A [96000] = 6666 [97000] = 10C5 DI = 3000 %3D BX = 3000 %3D ВР 3 С345 For the following instructions, determine the contents of AX after the each of the instruction has been executed: (а) MOV (b) MOV АХ, ВР АХ, [ВХ+DI] AX = AXarrow_forward(Part B) Design 32KW, 16-way set associative unblocked cache that has 8 bytes per word. Assume a 64 bit address. Calculate the following: (a) How many bits are used for the byte offset? (b) How many bits are used for the index field? (c) How many bits are used for the tag? (d) What is the physical size of each set (show as bits/row * # of rows, x * 2v)?arrow_forwardAVE THE CITY UNIVERSITY OF NEW YORK 4. (30%) We will be implementing a new instruction within the MIPS architecture. New instruction will decrement a Variable stored in a memory location and store the decremented value in a register (Rt). This new instruction will be called DECR. Its usage and interpretation is Usage: DECR Offset(4*Rs),Rt Interpretation:. Reg[Rt]= Mem[4*Rs+Offset] -1 Which blocks are used and which control signals are generated for this instruction. How would the Instrùction code fields look like ? Do we need to add an extra hardware logic, explain ? (You may draw a simplified datapath flow)arrow_forward
- 4. The following problems deal with translating from C code to MIPS code or MIPS code to C code. Assume that the signed variables f, g, h and i are assigned to registers $s0, $1, $2, $3 respectively. Assume the base address of the integer arrays A and B are in registers $s4 and $55 respectively. Translate the following MIPS code to C code. Please indicate which elements of integer array A and B are modified by this code. addi $t0, $1, 6 sll $t0, $t0, 4 add $t0, $t0, $5 Iw $t0, 0($t0) sw $t0, 4($4)arrow_forwardQ.No.8: In paging (given diagram), for CPU request there are two access time one for accessing page table and one for physical memory access. physical address f0000..0000 logical address CPU a) How should we minimize this access time? Redraw 1111...1111 the figure. b) Formulate the formula for Effective Access Time. c) Calculate Access Time (EAT) by assuming the Hit ratio (a ) the Effective physical memory 85% and 95%. Cache page table Access Time (ɛ) is 20 microsecond and Memory Access Time (T) is 100 microsecond.arrow_forward[4.3] Consider the following code: 1h x2, 0 (x10) sw x2, 8 (x10) Assume that the register x10 contains the address 0x80001000 and the data at address is OxABCDEF00. a. Write the required instructions to add the address 0x80001000 into the register x10? b. What value is stored in 0x80001008 on a little-endian machine?arrow_forward
- [3.3] For the following C statement, write the corresponding RISC-V assembly code. Assume that the variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29, respectively. Assume that the base address of the arrays A and B are in registers x10 and x11, respectively. B[8] A[i-j];arrow_forward1) Write simple instructions (simple program) that will add two consecutive bytes of data storied with offset locations NUM and NUM+1, store the result into the memory location NUM+2, using both: a- Direct addressing mode b- Indirect addressing mode or any mode 2) Write simple instructions (simple program) make 32-bit subtraction with Ax Bx Nol: No2: Cx Dx - [SI] [DI] Result: 3) Multiply Bl with the content of the memory location pointed by SI+30, store the result into Dx? 4) Divide Bx over 7, store the result into Bx? 5) Rebuild the instructions a- INC CX b- SUB AI,02H c- SUB AX,DX 6) Compare between SUB & CMP instructionsarrow_forwardarrow_back_iosSEE MORE QUESTIONSarrow_forward_ios
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