Microelectronics: Circuit Analysis and Design
Microelectronics: Circuit Analysis and Design
4th Edition
ISBN: 9780073380643
Author: Donald A. Neamen
Publisher: McGraw-Hill Companies, The
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Chapter 16, Problem 16.9EP

A CMOS inverter is biased at V D D = 1.8 V . The transistor parameters are V T N = 0.4 V , V T P = 0.4 V , K n = 200 μ A/V 2 , and K p = 80 μ A/V 2 . (a) Determine the transition points. (b) Find the critical voltages V I L and V I H , and the corresponding output voltages. (c) Calculate the noise margins N M L and N M H . (Ans. (a) V I t = 0.7874 V , V O P t = 1.187 V , V O N t = 0.3874 V ; (b) V I L = 0.6323 V , V I H = 0.8767 V , V O H U = 1.7065 V , V O L U = 0.1337 V ; (c) N M L = 0.4986 V , N M H = 0.8298 V )

(a)

Expert Solution
Check Mark
To determine

The transition points.

Answer to Problem 16.9EP

The transition parameter is VIt=0.7874V the transition parameter VOPt is 1.187V , the transition parameter VONt is 0.3874V .

Explanation of Solution

Given:

  VDD=1.8V

  VTN=0.4V , VTP=0.4V , Kn=200μA/V2 , and Kp=80μA/V2 .

Calculation:

The transition parameter of a CMOS inverter Vlt is,

  Vlt=VDD+VTP+KnKpVTn1++KnKp

Here, VDD is the biased voltage, VTP is the PMOS threshold voltage, VTN is the threshold voltage of the NMOS, Kn is the process parameter of NMOS, and Kp is the process parameter of the PMOS.

Substitute the values,

  Vlt=VDD+VTP+KnKpVTn1++KnKp=(1.8)+(0.4)+200μ80μ(0.4)1+200μ80μ=(1.8)+(0.4)+20080(0.4)1+200μ80μ=0.7874V

The transition parameter of a CMOS inverter VOPt is,

  VOPt=VltVTP

Substitute the values.

  VOPt=VltVTP=0.7874(0.4)=1.187V

The transition parameter of a CMOS inverter VONt is,

  VONt=VltVTN

Substitute 0.7874V for Vlt , and 0.4V for VTN .

  VONt=VltVTN=0.7874(0.4)=0.3874V

Conclusion:

Therefore, the transition parameter is VIt=0.7874V , the transition parameter VOPt is 1.187V , the transition parameter VONt is 0.3874V .

(b)

Expert Solution
Check Mark
To determine

The critical voltages VIL and VIH , and the corresponding output voltages.

Answer to Problem 16.9EP

The low critical voltage VIL is 0.6323V , the high critical voltage VIH is 0.8767V , the voltage VOHU at the point VIL is 1.7065V ,and the voltage VOLU at the point VIL is 0.1337V .

Explanation of Solution

Given:

  VDD=1.8V

  VTN=0.4V , VTP=0.4V , Kn=200μA/V2 , and Kp=80μA/V2 .

Calculation:

The low level critical voltage VlL is,

  VlL=VTN+(VDD+VTPVTN)(KnKp1)[2KnKpKnKp+31]

Substitute the values,

  VlL=VTN+(VDD+VTPVTN)(KnKp1)[2KnKpKnKp+31]=(0.4)+((1.8)+(0.4)(0.4))(200μ80μ1)[2(200μ)(80μ)200μ80μ+31]=(0.4)+((1.8)+(0.4)(0.4))(200801)[2(200)(80)20080+31]=0.6323V

The high level critical voltage VlH is,

  VlH=VTN+(VDD+VTPVTN)(KnKp1)[2KnKp3KnKp+11]

Substitute the values,

  VlH=VTN+(VDD+VTPVTN)(KnKp1)[2KnKp3KnKp+11]=(0.4)+((1.8)+(0.4)(0.4))(200μ80μ1)[2200μ80μ3200μ80μ+11]=(0.4)+((1.8)+(0.4)(0.4))(200801)[220080320080+11]=0.8767V

The output voltage VOHU at the point VIL is,

  VOHU=12[(1+KnKp)VIL+VDD(KnKp)VTNVTP]

Substitute the values,

  VOHU=12[(1+KnKp)VIL+VDD(KnKp)VTNVTP]=12[(1+200μ80μ)(0.6323)+(1.8)(200μ80μ)(0.4)(0.4)]=12[(1+20080)(0.6323)+(1.8)(20080)(0.4)(0.4)]=1.7065V

The output voltage VOLU at the point VIH is,

  VOLU=[(1+KnKp)VIH+VDD(KnKp)VTNVTP]2(KnKp)

Substitute the values,

  VOLU=[(1+KnKp)VIH+VDD(KnKp)VTNVTP]2(KnKp)=[(1+200μ80μ)(0.8767)(1.8)(0.4)(200μ80μ)(0.4)]2(200μ80μ)=[(1+20080)(0.8767)(1.8)(0.4)(20080)(0.4)]2(20080)=0.1337V

Conclusion:

Therefore, the low critical voltage VIL is 0.6323V , the high critical voltage VIH is

  0.8767V , the voltage VOHU at the point VIL is 1.7065V ,and the voltage VOLU at the point VIL is 0.1337V .

(c)

Expert Solution
Check Mark
To determine

The noise margins NML and NMH .

Answer to Problem 16.9EP

The low noise margin NML is 0.4895V , and the high noise margin NMH is 0.8298V .

Explanation of Solution

Given:

  VDD=1.8V

  VTN=0.4V , VTP=0.4V , Kn=200μA/V2 , and Kp=80μA/V2 .

Calculation:

The low noise margin NML is,

  NML=VILVOLU

Substitute 0.6323V for VIL and 0.1337V for VOLU

  NML=VILVOLU=(0.6232)(0.1337)=0.4895V

The high noise margin NMH is,

  NMH=VOHUVIH

Substitute 1.7065V for VOHU and 0.8767V for VlH

  NMH=VOHUVIH=(1.7065)(0.8767)=0.8298V

Conclusion:

Therefore, the low noise margin NML is 0.4895V , and the high noise margin NMH is 0.8298V .

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Chapter 16 Solutions

Microelectronics: Circuit Analysis and Design

Ch. 16 - Consider the NMOS logic circuit in Figure 16.18....Ch. 16 - Repeat Exercise TYU 16.5 for the NMOS logic...Ch. 16 - The CMOS inverter in Figure 16.21 is biased at...Ch. 16 - swA CMOS inverter is biased at VDD=3V . The...Ch. 16 - A CMOS inverter is biased at VDD=1.8V . The...Ch. 16 - Prob. 16.7TYUCh. 16 - Repeat Exercise Ex 16.9 for a CMOS inverter biased...Ch. 16 - Determine the transistor sizes of a 3input CMOS...Ch. 16 - Design the widthtolength ratios of the transistors...Ch. 16 - Design a static CMOS logic circuit that implements...Ch. 16 - Prob. 16.10TYUCh. 16 - Prob. 16.11TYUCh. 16 - Sketch a clocked CMOS logic circuit that realizes...Ch. 16 - Prob. 16.12EPCh. 16 - Prob. 16.13TYUCh. 16 - Consider the CMOS transmission gate in Figure...Ch. 16 - Prob. 16.15TYUCh. 16 - Prob. 16.14EPCh. 16 - Prob. 16.16TYUCh. 16 - Prob. 16.17TYUCh. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Sketch an NMOS threeinput NOR logic gate. Describe...Ch. 16 - Discuss how more sophisticated (compared to the...Ch. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Discuss the parameters that affect the switching...Ch. 16 - Prob. 6RQCh. 16 - Sketch a CMOS threeinput NAND logic gate. Describe...Ch. 16 - sDiscuss how more sophisticated (compared to the...Ch. 16 - Prob. 9RQCh. 16 - Sketch an NMOS transmission gate and describe its...Ch. 16 - Sketch a CMOS transmission gate and describe its...Ch. 16 - Discuss what is meant by pass transistor logic.Ch. 16 - Prob. 13RQCh. 16 - Prob. 14RQCh. 16 - Prob. 15RQCh. 16 - Describe the basic architecture of a semiconductor...Ch. 16 - ‘Sketch a CMOS SRAM cell and describe its...Ch. 16 - Prob. 18RQCh. 16 - Describe a maskprogrammed MOSFET ROM memory.Ch. 16 - Describe the basic operation of a floating gate...Ch. 16 - Prob. 16.1PCh. 16 - Prob. 16.2PCh. 16 - (a) Redesign the resistive load inverter in Figure...Ch. 16 - Prob. D16.4PCh. 16 - Prob. 16.5PCh. 16 - Prob. D16.6PCh. 16 - Prob. 16.7PCh. 16 - Prob. 16.8PCh. 16 - For the depletion load inverter shown in Figure...Ch. 16 - Prob. 16.10PCh. 16 - Prob. D16.11PCh. 16 - Prob. D16.12PCh. 16 - Prob. 16.13PCh. 16 - For the two inverters in Figure P16.14, assume...Ch. 16 - Prob. 16.15PCh. 16 - Prob. 16.16PCh. 16 - Prob. 16.17PCh. 16 - Prob. 16.18PCh. 16 - Prob. D16.19PCh. 16 - Prob. 16.20PCh. 16 - Prob. 16.21PCh. 16 - Prob. 16.22PCh. 16 - In the NMOS circuit in Figure P16.23, the...Ch. 16 - Prob. 16.24PCh. 16 - Prob. 16.25PCh. 16 - Prob. 16.26PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. D16.28PCh. 16 - Prob. D16.29PCh. 16 - Prob. 16.31PCh. 16 - Prob. 16.32PCh. 16 - Prob. 16.33PCh. 16 - Consider the CMOS inverter pair in Figure P16.34....Ch. 16 - Prob. 16.35PCh. 16 - Prob. 16.36PCh. 16 - Prob. 16.37PCh. 16 - Prob. 16.38PCh. 16 - Prob. 16.39PCh. 16 - (a) A CMOS digital logic circuit contains the...Ch. 16 - Prob. 16.41PCh. 16 - Prob. 16.42PCh. 16 - Prob. 16.43PCh. 16 - Prob. 16.44PCh. 16 - Prob. 16.45PCh. 16 - Prob. 16.46PCh. 16 - Prob. 16.47PCh. 16 - Prob. 16.48PCh. 16 - Prob. 16.49PCh. 16 - Prob. 16.50PCh. 16 - Prob. 16.51PCh. 16 - Prob. 16.52PCh. 16 - Prob. D16.53PCh. 16 - Figure P16.54 is a classic CMOS logic gate. (a)...Ch. 16 - Figure P16.55 is a classic CMOS logic gate. (a)...Ch. 16 - Consider the classic CMOS logic circuit in Figure...Ch. 16 - (a) Given inputs A,B,C,A,B and C , design a CMOS...Ch. 16 - (a) Given inputs A, B, C, D, and E, design a CMOS...Ch. 16 - (a) Determine the logic function performed by the...Ch. 16 - Prob. D16.60PCh. 16 - Prob. 16.61PCh. 16 - Prob. 16.62PCh. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Prob. D16.65PCh. 16 - Prob. 16.66PCh. 16 - Prob. 16.67PCh. 16 - The NMOS transistors in the circuit shown in...Ch. 16 - Prob. 16.69PCh. 16 - Prob. 16.70PCh. 16 - Prob. 16.71PCh. 16 - (a) Design an NMOS pass transistor logic circuit...Ch. 16 - Prob. 16.73PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. 16.75PCh. 16 - Prob. 16.76PCh. 16 - Prob. 16.77PCh. 16 - Consider the NMOS RS flipflop in Figure 16.63...Ch. 16 - Prob. 16.79PCh. 16 - Consider the circuit in Figure P16.80. Determine...Ch. 16 - Prob. D16.81PCh. 16 - Prob. 16.82PCh. 16 - Prob. 16.83PCh. 16 - Prob. 16.84PCh. 16 - (a) A 1 megabit memory is organized in a square...Ch. 16 - Prob. 16.86PCh. 16 - Prob. 16.87PCh. 16 - Prob. 16.88PCh. 16 - Prob. D16.89PCh. 16 - Prob. 16.90PCh. 16 - Prob. 16.91PCh. 16 - Prob. 16.92PCh. 16 - Prob. D16.93PCh. 16 - Prob. D16.94PCh. 16 - Prob. D16.95PCh. 16 - An analog signal in the range 0 to 5 V is to be...Ch. 16 - Prob. 16.97PCh. 16 - Prob. 16.98PCh. 16 - Prob. 16.99PCh. 16 - The weightedresistor D/A converter in Figure 16.90...Ch. 16 - The Nbit D/A converter with an R2R ladder network...Ch. 16 - Prob. 16.102PCh. 16 - Prob. 16.103PCh. 16 - Prob. 16.104PCh. 16 - Prob. 16.105PCh. 16 - Design a classic CMOS logic circuit that will...Ch. 16 - Prob. D16.111DPCh. 16 - Prob. D16.112DPCh. 16 - Prob. D16.113DP
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