The circuit parameters of the diff-amp shown in Figure 11.2 are V + = 3 V , V − = − 3 V , and I Q = 0.25 mA . Base currents are negligible and V A = ∞ for each transistor. (a) Design the circuit such that a differential-mode output voltage of v o = v C 1 − v C 2 = 1.2 V is produced when a differential-mode input voltage of v d = v 1 − v 2 = 16 mV is applied. (b) What is the maximum possible common-mode input voltage that can be applied such that the input transistors remain biased in the forward-active mode? (c) For a one-sided output, what is the value of CMRR dB if the output resistance of the current source is R o = 4 M Ω ?
The circuit parameters of the diff-amp shown in Figure 11.2 are V + = 3 V , V − = − 3 V , and I Q = 0.25 mA . Base currents are negligible and V A = ∞ for each transistor. (a) Design the circuit such that a differential-mode output voltage of v o = v C 1 − v C 2 = 1.2 V is produced when a differential-mode input voltage of v d = v 1 − v 2 = 16 mV is applied. (b) What is the maximum possible common-mode input voltage that can be applied such that the input transistors remain biased in the forward-active mode? (c) For a one-sided output, what is the value of CMRR dB if the output resistance of the current source is R o = 4 M Ω ?
Solution Summary: The author explains the design of the circuit fulfilling the given conditions. The base currents are negligible and V_A=infty.
The circuit parameters of the diff-amp shown in Figure 11.2 are
V
+
=
3
V
,
V
−
=
−
3
V
,
and
I
Q
=
0.25
mA
.
Base currents are negligible and
V
A
=
∞
for each transistor. (a) Design the circuit such that a differential-mode output voltage of
v
o
=
v
C
1
−
v
C
2
=
1.2
V
is produced when a differential-mode input voltage of
v
d
=
v
1
−
v
2
=
16
mV
is applied. (b) What is the maximum possible common-mode input voltage that can be applied such that the input transistors remain biased in the forward-active mode? (c) For a one-sided output, what is the value of
CMRR
dB
if the output resistance of the current source is
R
o
=
4
M
Ω
?
In the push-pull stage given (in the photo attached), IS1 = 5 × 10−17 A and IS2 = 8 × 10−17 A. Calculate the value of VB so as to establish a bias current of 5 mA in Q1 and Q2 (for Vout = 0).
If the peak input swing is 2 V and RL = 8Ω :
Calculate the small-signal voltage gain for Vout ≈ 0
Use the gain obtained in (i) to estimate the output voltage swing.
Estimate the peak collector current of Q1 assuming that Q2 still carries 5 mA
For the differential amplifier circuit below, all transistors are identical ( ?≠0 )
a) Draw the single-sided differential mode equivalent circuit, showing all details and labels Explain how you obtained this equivalent circuit
The given circuit is a 2N4403 PNP common collector amplifier. Let VCC=12V, VEE=-12V, R1=52.5kΩ, R2=33kΩ, and RE=2.5kΩ. Determine IB, IC, IE, VB, VC, and VE. Start by initially assuming |VBE| =0.7V or and assuming a value of beta (β). Where to look for the value of β? (Hint: It’s in the transistor model assigned). Determine the input voltage (may extend from the supply voltage range) where the BJT goes from “cut-off to active” and where it goes from “active to saturation”. Assume VCE=0.3V (edge of saturation), RL=500Ω, and C1, C2→∞.
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