Redesign the circuit in Figure 11.30 using a Widlar current source and bias voltages of ± 5 V . The bias current I Q is to be no less than 100 μ A and the total power dissipated in the circuit (including the current-source circuit) is to be no more than 10 mW . The diff-amp transistor parameters are the same as in Exercise Ex 11.10 . The circuit is to provide a minimum loading effect when a second stage with an input resistance of R = 90 k Ω is connected to the diff-amp. Determine the differentialI mode voltage gain for this circuit. (Ans. R 1 = 10.3 k Ω , R E = 0.571 k Ω , A d = 158 ).
Redesign the circuit in Figure 11.30 using a Widlar current source and bias voltages of ± 5 V . The bias current I Q is to be no less than 100 μ A and the total power dissipated in the circuit (including the current-source circuit) is to be no more than 10 mW . The diff-amp transistor parameters are the same as in Exercise Ex 11.10 . The circuit is to provide a minimum loading effect when a second stage with an input resistance of R = 90 k Ω is connected to the diff-amp. Determine the differentialI mode voltage gain for this circuit. (Ans. R 1 = 10.3 k Ω , R E = 0.571 k Ω , A d = 158 ).
Solution Summary: The author explains the design parameters of the circuit using a Widlar current source to meet the specifications.
Redesign the circuit in Figure 11.30 using a Widlar current source and bias voltages of
±
5
V
. The bias current
I
Q
is to be no less than
100
μ
A
and the total power dissipated in the circuit (including the current-source circuit) is to be no more than
10
mW
. The diff-amp transistor parameters are the same as in Exercise
Ex
11.10
. The circuit is to provide a minimum loading effect when a second stage with an input resistance of
R
=
90
k
Ω
is connected to the diff-amp. Determine the differentialI mode voltage gain for this circuit. (Ans.
R
1
=
10.3
k
Ω
,
R
E
=
0.571
k
Ω
,
A
d
=
158
).
Refer to the differential amplifier circuit shown below .
Determine the quiescent DC voltage at the collector terminal of each transistor assuming VBE of two transistor are negligible.
What will be the quiescent DC values if VBE is taken to be 0.7 V.
a.) Consider a two-BJT configuration in Figure 1. You may assume that both transistors are the same with the same β, VBE,on = 0.7 V, and VCE,EOS = 0.3 V. Determine the minimum voltage VBE that will turn ON both Q1 and Q2.
b.) Using the BJT small-signal model given in Figure 2, determine the AC current gain Ai = iout/iin for the circuit given in Figure 3. Assume ro >> rπ. You may assume that β is large.
For the class B output stage of Figure 2, let ??? = 6 V and ?? = 4Ω. If the output is a
sinusoidal with 4.5V peak amplitude, find;
(a) The output power.
(b) The average power drawn from each supply/
(c) The power efficiency obtained at this output voltage.
(d) The maximum power that each transistor must be capable of dissipating safely.
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